logoalt Hacker News

bpye10/12/20242 repliesview on HN

The coreboot docs claim that modern AMD parts no longer support cache-as-RAM.

https://doc.coreboot.org/soc/amd/family17h.html


Replies

hales10/12/2024

Wow, thanks for the link, I had no idea:

> AMD has ported early AGESA features to the PSP, which now discovers, enables and trains DRAM. Unlike any other x86 device in coreboot, a Picasso system has DRAM online prior to the first instruction fetch.

Perhaps they saw badly trained RAM as a security flaw? Or maybe doing it with the coprocessor helped them distribute the training code more easily (I heard a rumour once that RAM training algos are heavily patented? Might have imagined it).

SV_BubbleTime10/12/2024

Lame.

Using it as TCM ram seems super useful.

Although you would need to fight/request it from the OS, so technically I see why they might ditch it.