The reason why Cadence and Synopsys do not have concurrence is that there are no open PDKs for modern technologies.

The existing open PDKs are for technologies from 20 years ago.

If TSMC, Intel, Samsung, or even Global Foundries or other second tier foundry would publish the design rules for their manufacturing processes and specifications of the formats for the product documentation that they must receive from a customer, it would be easy to make something better than the overpriced commercial tools.

I have used for many years the tools provided by Cadence, Mentor and Synopsys, so I know with certainty that it would be easy to improve on them if only one would have access to the documents kept secret by TSMC and the like.

This collusion of the foundries with the EDA vendors that eliminates the competition from the EDA market does not make much sense. Normally better and cheaper design tools should only bring more customers to the foundries, so I do not understand what do they gain from the status quo. (Unless they fear that public documentation could make them vulnerable to litigation from patent trolls.)

Fear of competition in the foundry market cannot be the reason for secret design rules. There is negligible competition in the foundry market and the most dangerous competitor of TSMC is Intel. Yet TSMC makes now chips for Intel, so the Intel designers have seen much of the TSMC design rules and they could chat about them with their buddies from the Intel foundry division. So TSMC must not give great importance in keeping the design rules secret from direct competitors. Therefore they must keep the rules secret mainly for other parties, but I cannot guess who are those.