> in my experience they are not that much difference between 2 design.

Depends!

If the two chips use UART or SPI for intercommunication, okay, you need two lines between the CPU and two GPIO lines for wakeup, and JTAG can be shared anyway.

But if you use stuff like shared memory, or want to do stuff like updating the display not just from the high-power chip but also from the low-power one, suddenly design becomes much more complex.