Chisel can be compiled to Verilog out of the box, and Verilog itself should have the required support from existing EDA tools. That remark from the paper may perhaps be somewhat confused.

> Isn't translating between languages something that LLMs should excel at?

No, not at all. Unless there is a large amount of training data relevant to the translation then LLMs are likely just to make up nonsense. Chisel is a very niche hardware description language.

I'm not sure this sentence [from the paper] makes a lot of sense. The only thing non-standard is the use of Chisel (and then probably CIRCT to lower it into Verilog) - if you're actually taping these out, you're still feeding that to industry-standard EDA tools.

you really really REALLYYY don't want an llm involved anywhere near this stuff. Hardware bugs are notoriously expensive (see pentium fdiv bug).

To the contrary, it's something especially suited to being done parametrically. Effectively, you can make a really big regex string to convert one language into a subset of another, then let the optimizer of the second language make it performant.