>386 has eight pins labeled "NC" (No Connect)

and Cyrix 486DLC hijacks 7 of those :)

A20M# (F13) - when supported by motherboard you can L1 cache whole ram instead of leaving first 64KB uncached

FLUSH# (E13) - when supported by motherboard you dont have to use hacks and flush L1 on every DMA access. Hacks (BARB mode) seemed clever at the time until everyone had a Sound Blaster DMAing audio constantly invalidating cache while gaming.

RPLSET (C6) RPLVAl (C7)- L1 cache status debug outputs

SUSP# (A4) SUSPA# (B4)- suspend support, wakes on INT and NMI. Good for laptops.

>The surprising thing is that one of the No Connect pads does have the bond wire in place

Somehow Cyrix picked this particular pin (B12) for KEN# input (enable L1 cache) :O

>From the circuitry on the die, this pin appears to be an output

Meaning the _one_ NC pin Intel CPU actually wires, an output no less, Cyrix demands driven low to enable cache.