LHC's New Chip Tackles Radiation Challenges

I was curious about the analog to digital converter stages, and how it would fare in the radiation.

Turns out they're a bit lucky I guess. As noted in the paper[1]:

Transient errors affecting one or a few data samples due to SEUs can be tolerated and corrected by offline data analysis since the LAr pulse shape is analytically known.

This was used in their design:

The architecture incorporates a 9-subrange (3.2 bits) MDAC before a 12-bit, two-stage SAR, with the MDAC used to relax the dynamic range requirement for the SAR.

The MDAC and SAR are memory-less and their states are determined by the 40-MHz precision sampling clock and an intermediate 80-MHz internal clock signal. Therefore, any radiation-induced upset will only affect an individual sample.

[1]: https://ieeexplore.ieee.org/document/11017335

Title of the article starts with "Large Hardon Collider". I can't think of anything quippy to add, but that's not how "Hadron" is spelled.