Designing a Low Latency 10G Ethernet Core (2023)

LinkedIn tells me: https://uk.linkedin.com/in/ttchisholm

    FPGA engineer with a focus on ultra-low latency networking at Jane Street.

It seems fun to be a high frequency FPGA trader designer. All my FPGA is much lower power consumption so I don't get to play with stuff like gigs of external SRAM or the QDR stuff or whatnot

less than 60ns loopback latency

There are some Ethernet switches with 4ns latency, and those do more than just sending and receiving, so there's clearly still an order of magnitude of improvement still available. 4ns is basically ~40 cycles of the bit clock for 10G Ethernet.