alt Hacker News>The Neoverse V3 and Cortex-X4 cores are very similar in size and performance with the Intel E-cores Skymont and Darkmont (the E-cores of Arrow Lake and of the future Panther Lake).
That is not entirely accurate. X4 is big core design. All of its predecessor and successor has always had >1mm2 die space design. X4 is already on the smaller scale, it was the last ARM design before they went all in chasing Apple's A Series IPC. IRRC it was about 1.5mm2 depending on L2 cache. E-Core for Intel has always been below 1mm2. And again IRRC that die size has always been Intel's design guidelines and limits for E-Core design.
More recent X5 / X925 and X6 / X930 / C1 Ultra?? ( I can no longer remember those names ) are double the size of X4. With X930 / C1 Ultra very close to A19 Pro Performance. Within ~5%.
I assume they stick with X4 is simply because it offers best Performance / Die Space, but it is still a 2-3 years old design. On the other hand I am eagerly waiting for Zen 6c with 256 Core. I cant wait to see the Oxide team using Zen 6c, forget about the cloud. 90%+ of companies could fit their IT resources in a few racks.
Nope. Cortex-X4 is not a big core design, though you are right that at the time of its launch in 2023 the Arm company was not offering bigger cores yet.
The cores designed now by the Arm company for non-embedded applications are distributed into 4 sizes, of which the smaller 2 sizes correspond to what were the original "big and little sizes", but what was originally the big size has been continued into what are now medium-to-small cores, and the last such core before the rebranding was Cortex-A725.
Cortex-X4 is of the second size, medium-to-large. Cortex-X925 was the last big core design before Arm changed the branding this year, so several recent smartphones use Cortex-X925 as the big core, Cortex-X4 as the medium-sized core and Cortex-A725 as the small cores, omitting the smallest Cortex-A520 cores.
Cortex-X4 and Intel Skymont have exactly the same size, 1.7 square millimeter with 1 MB L2 cache memory (in Dimensity 9400 and Lunar Lake). This is about a third of the area of a big core like an Intel P-core and less than a half of the area of a Zen 5 compact core (but AMD uses an older less dense CMOS process; had AMD also used a "3 nm" process the area ratio would not have been so great, and Zen 5 has a double throughput for array operations).
Moreover, Neoverse V3/Cortex-X4 and Intel Skymont/Darkmont have approximately the same number of execution units of each kind in their backends. Only their frontends are very different, which is caused by the different ISAs that must be decoded, Aarch64 vs. x86-64.
The last Arm big core before rebranding, Cortex-X925, was totally unsuitable as a server core, as it had very poor performance per area, having a double area in comparison with Cortex-X4, but a performance greater by only a few tens percent at most. Therefore the performance per socket of a server CPU would have been much lower than that of a Graviton5, had it been implemented with Cortex-X925, due to the much lower number of cores per socket that could have been achieved.
Cortex-X4 was launched in 2023 and it was the big core of the 2024 flagship smartphones, then it has become the medium core of the 2025 flagship smartphones. Its server variant, Neoverse V3, has been launched in 2024 and it has been deployed in products only this year, first by NVIDIA (in Orin) and now by AWS.
It is not at all an obsolete core. As I have said, Intel will have only next year a server CPU with E-cores as good as Cortex-X4. We do not know yet any real numbers about the newly announced Arm cores that have replaced Cortex-A520, Cortex-A725, Cortex-X4 and Cortex-X925, so we do not know if they are really significantly better. The numbers used by Arm in presentations cannot be verified independently and usually when the performance is measured much later in actual products it does not match the optimistic predictions.
The new generation of cores might be measurably better only for computational applications, because they now include matrix execution units, but their first implementation may be not optimal yet, as it happened in the past with the first implementation of SVE, when the new cores had worse energy efficiency than the previous generation (which was corrected by improved implementations later).