What mistakes?
No one is ever going to design an ISA that is complete and finished forever on Day #1. There are always going to be new data types and new algorithms to support e.g. the current rush to add "AI" support to all ISAs (NPUs, TPUs, whatever you want to call them).
Arm has ARMv9-A following on from ARMv8-A, and they are already up to Armv9.7-A in addition to as many ARMv8-A enhancements.
Intel/AMD have all kinds of add-ons to x86_64, and not even linear e.g. the here now gone now AVX512. Finally here to stay (presumably) in x86-64-v4. And there is already APX and AVX10 to add to that.
If people standardized around something like the RISC-V X280, added some standard license-free hardware codecs, and quietly ejected every other distraction. Than RISC-V may have dropped into mobile SoC markets like amd64 did with x86 hard-to-use failed successor IA-64. Note, the silicon business is about selling sustained volumes of identical product, and not about a CEOs ego selling bespoke chips in sub 100k batches.
There were many great chips that never survived in consumer product spaces. When manufacturers tell chip houses there is a permutation compatibility risk issue, and people take a petulant stance on the feedback... “Not my circus, not my monkeys” as they say.
1. Intel is kept alive by the promise of an integrated NVIDIA RTX SoC.
2. AMD understood something important about the software market, and that was easy backward-compatibility wins over _every_ other feature. Even Intel had to learn this the hard way.
3. 93% of the market is change sensitive... anyone that assumes cross-compiling is on the queue for that sector is greatly mistaken. Note, it took ARM over a decade driven by Googles dominance with mobile to gain traction.
4. Most software libraries will only enable advanced chip features if hardware is detected, and most compiled code simply uses the compatibility subset of compiled features (sure its 3 times slower, but it works everywhere.) No one is going to go through every permutation of an ISA with vendor specific features. The NERF'd subset of features in most Aarch64 and amd64 packages should be enough indication software people won't give a bean about unstable vanity silicon features.
We shall see how RISC-Y plays out in the market. Old Yeller sure looks nervous. =3