alt Hacker News> This increases the maximum core count per chiplet from 8 to 12. Furthermore, it increases the L3 cache per CCX/CCD from 32 MB to 48 MB.
I'd say the amount of L3 is not increased but adapted/scaled to the increased core count, since per each core there is still the same amount of cache available as before.
We get faster cores, so we need to get from 5600 to e.g. 6000 DDR5. Since core count is increased by 50%, we'd need 9000... DDR5^W, well yes, we'd need actually as planed before AM6 and DDR6!
There are already DDR5 CUDIMMs at and above 8000 MT/s, and 9600 MT/s has been demonstrated but none are currently in stock. By the time AMD ships Zen 6 desktop processors, the market should be ready with memory modules that will mean even the highest core count Zen 6 parts will be at worst only slightly more bandwidth-starved than their predecessors. And the lower core count Zen 6 CPUs with a single CCD should be able to provide substantially more bandwidth than their predecessors. All without requiring DDR6 yet.