CES 2026: Taking the Lids Off AMD's Venice and MI400 SoCs

> this would be the first time that a high core count CCD will have the ability to support a V-Cache die. If AMD sticks to the same ratio of base die cache to V-Cache die cache, then each 32 core CCD would have up to 384MB of L3 cache which equates to 3 Gigabytes of L3 cache across the chip.

Good lord!

> CCD

Core Complex Die - an AMD term for a chiplet that contains the CPU cores and cache. It connects to an IOD (I/O die) that does memory, PCIe etc (≈southbridge?).

Aside: CCX is Core Complex - see Figure 1 of https://www.amd.com/content/dam/amd/en/documents/products/ep...

For any other older fogeys that CCD means something different.

256 cores on a die. Stunning.

I'd just like to take a moment to appreciate chipsandcheese and how they fill the Anandtech-shaped void in my heart <3

random internet feedback:

i really wish the article would have spent 2 sec to write in parenthesis what 'ccd' is (its 'Core Complex Die' fyi)

How is this sort of package cooled? Seems like you'd pretty much need to do some sort of water cooling right?

256c/512t off a single package… likely 1024 threads in a 2cpu system.

Basically we are about to reach the scale where a single rack of these is a whole datacenter from the nineties or something like that

The new double wide rack looks good

AMD Venice? 2005 is calling!

x86_64 server architecture 256 cores on a die.

Blackwell 100+200 compression spin lock documentation.

Have not checked for a while, but does AMD at this point have any software to run stable and efficiently?

Or are they still building chips no one wants to use because cuda is the only thing that doesn’t suck balls