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sylwareyesterday at 11:45 AM3 repliesview on HN

I wish I could buy RP2350 with the ARM cores being hard-fused disabled, "cheaper" since no ARM royalties would have to be paid.

That said, I wonder how much they did improve their hazard3 design, because we all know the future is no PI locked ARM cores. I wonder if they are sharing part of the design of other open source RISC-V cores.

If those efforts are kept significant, the future is looking good and better there. Hopefully, all that will be a success (=latest silicon process, ultra-performant RISC-V implementation in mobile/embedded/desktop/server).


Replies

danhoryesterday at 12:24 PM

The Hazard 3 is basically a hobby project of Luke Wren, a Raspberry Pi Employee. He's contiuing to evolve it further, but I don't think it's ready for a full replacement of the Cortex-M yet, especially in regards to the Security Features.

The source code is all from Luke Wren and I don't think other cores use the source code directly, but improvements to test harnesses or general implementation patterns as well as better software support help other cores: https://github.com/Wren6991/Hazard3

For the SoCs I would expect to see an off-the-shelf Risc-V core (certainly no Hazard3 as the main CPU), but we'll see.

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Tharreyesterday at 12:49 PM

You can probably already get that if you order a somewhat significant amount of chips directly from Raspberry Pi. They seem to already have everything required for it, it's literally just setting a bit differently during factory programming.

But I'm assuming you're talking about for consumer use, in which case my question is why? There is absolutely no way you're ever benefiting from them spinning up an extra SKU with significantly less volume (most people want the ARM cores).

Even if they decide to eat the costs for the benefit of consumers, at most the chip would be what, 15 cents cheaper? I really struggle to see how that's a meaningful difference for hobbyist use.

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phkahleryesterday at 2:02 PM

>> I wish I could buy RP2350 with the ARM cores being hard-fused disabled, "cheaper" since no ARM royalties would have to be paid.

Better yet, put 4 RISC-V cores on there!

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