alt Hacker NewsI’m curious why you don’t target an HDL, which seems like it should match very well to llm capabilities, and rely on existing layout solvers for describing the last physical layout step?
I’m curious why you don’t target an HDL, which seems like it should match very well to llm capabilities, and rely on existing layout solvers for describing the last physical layout step?
This seems to be a discussion about board level circuits. HDLs are for chip design.
So far the language models aren’t great at HDL but I assume it’s just a training priority thing and not some characteristic of HDLs.