> So parent was 'wrong' that "chiplets" were ever called MCM's. But right that "chips designed with multiple chiplet-looking-things" did used to be called "MCM's".

No, chiplets were called MCMs. IBM and others as you noted had chip(lets) in MCMs that were not "fully-functioning" by themselves.

> Also MCM's lacked the kind of high-bandwidth, low-latency fabric for CPU's to communicate more directly with each other. For the Pentiums, that was organic substrates (the usual green PCB material) and routing copper traces between the dies. For the IBM's, that was an advanced ceramic-glass substrate, which had much higher bandwidth than PCB traces but still required a lot of space to route all the copper traces (latency taking a hit) and generated a lot of heat. Today we use silicon for those interconnects, which gives exemplary bandwidth+latency+heat performance.

This all just smells like revisionist history to make the name be consistent with previous naming.

IBM's MCMs had incredibly high bandwidth low latency interconnects. Core<->L3 is much more important and latency critical than core+cache cluster <-> memory or other core+cache cluster, for example. And IBM and others had silicon interposers, TSVs, and other very advanced packaging and interconnection technology decades ago too, e.g.,

https://indico.cern.ch/event/209454/contributions/415011/att...

The real story is much simpler. MCM did not have a great name particularly in consumer space as CPUs and memory controllers and things consolidated to one die which was (at the time) the superior solution. Then reticle limit, yield equations, etc., conspired to turn the tables and it has more recently come to be that multi chip is superior (for some things), so some bright spark probably from a marketing department decided to call them chiplets instead of MCMs. That's about it.

Aside, funnily enough IBM actually used to (and may still), and quite possibly others, actually call various cookie cutter blocks in a chip (e.g., a cluster of cores and caches, or a memory controller block, or a PCIe block), chiplets. From https://www.redbooks.ibm.com/redpapers/pdfs/redp5102.pdf, "The most amount of energy can be saved when a whole POWER8 chiplet enters the winkle mode. In this mode, the entire chiplet is turned off, including the L3".