alt Hacker Newsdigital circuit design strikes me as a risky gambit for a career, given that almost everyone who ive bumped into in that industry was invariable not actually doing any design, but rather was tasked with writing test cases and verifying the functionality of some specific logical block.
tests are ofcourse very important, but fact of the matter is, bright smart and arrogant young engineers-to-be are very eager to show everyone how much better their version of the 'thing' is, and desperately want to write their version of the thing: they don't want to verify someone else's version of the thing.
if we're being honest, how many people do you really need to do the design of some hardware feature? realistically the design can be done by one person.
so you might have one lead designer, delegates each block to 10 guys, and everything else is basically 'monkey work' of writing up the state machine logic, testing it, and hooking it all up.
and now lets count the number of companies that can put up the capital for tape-out: amd, intel, arm, nvidia, meta, aws, google chips, apple, and lets say plus 50 for fintechs, startups, and other 'smaller' orgs.
so if you want to do design, you might be competing for... lets say 3 lead designers per org on avg, 3 * 50 = 150 silicon design spots for the entire globe. to add, a resource in such scarce supply will no doubt be heavily guarded by its occupants.
i did this calculation back when i was still in uni. i'll never know if it paid off, or if it was even rooted in logic, but i remember thinking to myself back then: "no way in hell am i gonna let these old guys pidgeon hole me into doing monkey work with a promise of future design opportunities." arrogant, yes, but i can't say i regret my decision judging from the anecdotes i get from friends in the hardware world.
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some additional thoughts:
i think that, for digital design to be interesting, the cost of entry must be lowered by probably orders upon orders of magnitude.
the google skywaterpdk thing, whatever it is (or was?), did produce a great deal of hobbyist designs and proved that there really isn't anything special about rtl - infact, its really quite monotonous and boring.
which is a good attitude to have, really. lots of hobbyist designs got cranked out quickly on what, as i understood, was a very obsolete pdk from two decades ago.
but its fundamentally still too expensive and too limited. open source software 'blew up' because
1. the cost of entry was free...
2. ...for state of the art tools.
its not enough to be free, or open source. it also has to be competitive. llvm/gcc won the compiler world because they blew the codegen of proprietary compilers out of the water, ofcourse being open source it became a positive feedback loop of lots of expert eyeballs -> better compiler -> more experts look at it -> better compiler -> ...
for digital design to become interesting, you can't trick the kids: they want the same tech the 'big boys' are using. so, what scope is there to make it economical for someone like Intel carving out some space for a no-strings-attached digital design lottery?
i get the impression that, unlike for most manufacturing processes, the costs of silicon digital electronics increases every year, and the amortisation schedule becomes bigger, not smaller.
so if anything, it seems that the more high tech silicon manufacturing becomes, the smaller the pool of players (who have the ever-increasing capital expenditure necessary) becomes, which should indicate that the opportunities for digital design work are actually going to be shrinking as time goes on.
> and now lets count the number of companies that can put up the capital for tape-out: amd, intel, arm, nvidia, meta, aws, google chips, apple, and lets say plus 50 for fintechs, startups, and other 'smaller' orgs.
And basically anyone who has a job in tech [1] or someone who just pulled their salary out of the ATM has enough money to do a tapeout with the cash in their hand [2] or chinese students for basically free[3]. Of course, for _some_ scopes of tapeout. These are older nodes and you have limited area. But you might not need anything fancy for your design.
The rest of the post, I think has a bunch of misunderstandings or wrong facts, but I don't work in the field, (ish) so I might be as clueless as you and I need to get back to my day job so I won't try countering you just yet.
[1] https://wafer.space/ [2] https://app.tinytapeout.com/calculator?tiles=1&pcbs=1 [3] https://ysyx.oscc.cc/docs/en/