> RISC-V doesn't have the pitfalls of Sparc (register windows, branch delay slots),

You're saying ISA design does have implementation performance implications then? ;)

> There's no one that expects it'll be hard to optimize for

[Raises hand]

> There are at least 2 designs that have taped out in small runs and have high end performance.

Are these public?

Edit: I should add, I'm well aware of the cultural mismatch between HN and the semi industry, and have been caught in it more than a few times, but I also know the semi industry well enough to not trust anything they say. (Everything from well meaning but optimistic through to outright malicious depending on the company).