How are FPGAs "bruned into silicon"? Would be news to me that there are ASICs being taped out at CERN
CERN in fact does design custom ASICs for other things: https://indico.cern.ch/event/1115079/contributions/4693643/a...
(Probably not for this here though.)
Could they.... have someone else do it for them?
alt Hacker News
CERN in fact does design custom ASICs for other things: https://indico.cern.ch/event/1115079/contributions/4693643/a...
(Probably not for this here though.)