Draw yourself an SR latch and try simulating. Or a circuit what is known as „pulse generator“
Both SystemVerilog and VHDL have AMS extensions for simulating analog circuits. They work pretty well but you also pay a pretty penny for the simulator licenses for them.
Those are analog circuits, if you put them in your digital design you are doing something wrong.
Both SystemVerilog and VHDL have AMS extensions for simulating analog circuits. They work pretty well but you also pay a pretty penny for the simulator licenses for them.