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UltraSanetoday at 4:32 AM2 repliesview on HN

The clever part is figuring out what RAM is controlled by which controllers.


Replies

saidnooneevertoday at 8:23 AM

everyone says this but no one says why it was clever. i find her videos have cool results but i cant have patience for them usually because its recycled old stuff (can be cool but its not ground breaking).

there is a ton of info you can pull from: smbios, acpi, msrs, cpuid etc. etc. about cpu/ram topology and connecticity, latencies etc etc.

isnt the info on what controllers/ram relationships exists somewhere in there provided by firmware or platform?

i can hardly imagine it is not just plainly in there with the plethtora info in there...

theres srat/slit/hmat etc. in acpi, then theres MSRs with info (amd expose more than intel ofc, as always) and then there is registers on memory controller itself as well as socket to socket interconnects from upi links..

its just a lot of reading and finding bits here n there. LLms are actually really good at pulling all sorts of stuff from various 6-10k page documents if u are too lazy to dig yourself -_-

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kzrdudetoday at 10:01 AM

I have to say that using drawbridges and differently colored rail pieces to explain it was very clever.