The graphs towards the end were discharge curves for a single transistor/capacitor cell out of only 16 present, if I understood correctly? So "enough cells to count as memory" and "addressing logic" are definitely future work (it looked like he wanted to characterize what the refresh cycle would have to look like before actually building more.) I was kind of surprised that the "use a microscope as a photolithography projector" approach worked at all, it will be interesting to see how that scales up...