Indeed!! MIPS - $zero RISC-V - x0 SPARC - %g0 ARM64 - XZR

lynguist • today at 8:10 AM • 2 replies • view on HN

Indeed!!

MIPS - $zero

RISC-V - x0

SPARC - %g0

ARM64 - XZR

classichasclass • today at 1:02 PM

PowerPC: "r0 occasionally" (with certain instructions like addi, though this might be better considered an edge case of encoding)

matja • today at 3:22 PM

Alpha: r31, f31

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