This is probably a good place to debunk the usual wisdom that "decoupling capacitors must be placed very close to the IC pins". If you're using a solid power plane, rather than routing power through traces (and honestly 4/6 layer boards are cheap enough these days) it really doesn't matter where you place decoupling capacitors for most uses - keep the via traces short or ideally in the pad, and you can put all your decoupling capacitors in one place on the boards a way away from the chip and focus on good routing of your signals. Figure 15 on this paper (and the whole paper!) explains it well: https://scholarsmine.mst.edu/cgi/viewcontent.cgi?article=221...
Great paper!. Anyonw know whether there are any modern tools/software that can simulate this during design?