I am coding assembly using the static code prediction rule (on RISC-V): if not registered in the predictor, conditional forward branch is predicted not taken and contitional backward branch is predicted taken.

Mechanically, it pushes down forward the 'unlikely' code, and with semantic knowledge of how 'hot' a code is, you can, very easily hierarchically refactor (assembly) code to really favor the 'likely' code, that in a intensity spectrum.

Basically speaking, mostly all 'expected' code will be nicely packed and predicted, and you can do that at various scale (yes, it works for huge code paths).

It is beautiful :)

I wonder if x86_64 hardware follows that rule (I think I read it for intel, but not AMD).