I've used AI successfully for some things but for SystemVerilog it's pretty rubbish. Too little training data I assume, and everything is behind firewalls.
However it's not completely useless - I've used it successfully for boilerplate for small demos and bug reproducers... And it has clarified some things for me (obviously I double checked what it said with the LRM). So I guess it's fair to say that they have "shown promise", in the same way that my 6 year old shows promise.
AI is advancing so quickly though, I bet it will be pretty good in a few years.
> RTL is not code
Of course it is. It executes on an unusual machine, but it's clearly code. I'll never understand this "hardware design is totally unlike software design" attitude that hardware designers have. Is it just so they feel special? They're really quite similar.
> RTL is not code
>>Of course it is.
most programming languages have that one serious key property that Ive mentioned above - ABSTRACTION. you can well reason about a function that calls another function addTheseTwoStranegObjectsTogether(arg, arg2) and make totally valid assumptions on how and what would happen. "executing" that code is a depth first call graph walk, pretty linear one too. You cannot do these things by reading RTL code, the state space is enormous, there is no "unusual machine" that executes it (if you mean simulators, thats a different thing). also you cannot reason even about simplest instances since they are stateful and that is in no way is exposed via interface connections
>AI is advancing so quickly though, I bet it will be pretty good in a few years.
Time will tell :) Cheers