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elevationtoday at 3:04 PM6 repliesview on HN

Why couldn't a company committed to mask fabrication and wafer fabrication, in concept, perform these steps daily, or several times daily? Multiple prototype designs could be grouped together so multiple customers can realize a new design instance in the same iteration.

With an appropriate debug core in the same wafer, designers who'd completed a tape-out could connect to their chip well enough to repeat their design-verification tests on this real hardware, remotely even (no need to physically handle the device 'til you're certain it's working.) Once satisfied, customers could promote their design to be bonded out for installation into their PCB.

"Sure thing boss, we'll add an extra USART core to this afternoon's tape out."


Replies

jimmyswimmytoday at 6:30 PM

The iteration cycles are limited necessarily by the time between tapeout and getting chips off the line to a testable state. Maybe there's a little room to get an in-wafer test probe system built at the fab if each die has a standard pad layout, which would speed up the 'testable state' part of that timeline. But if your timeline is weeks (if only!) to months, there's little utility in being able to make incremental changes on a daily basis.

Plus, the only way fab costs become achievable are MPW runs which don't have adequate demand for multiple daily runs. The ones I've used run a few processes each month, rotating between most of them on a bimonthly to quarterly basis. They just don't fill up fast enough. But I'm small time fabless so maybe I'm missing something.

elictronictoday at 3:35 PM

Because you are dealing with the physical world where those different designs have different requirements that can conflict. It’s like saying all software is basically the same, why don’t you just abstract it all and run it on these Raspberry Pi’s.

You can do that, but it’s going to turn out poorly.

monocasatoday at 3:18 PM

The wafer manufacturing process takes weeks to months after a tape out.

show 1 reply
bee_ridertoday at 3:49 PM

I sort of expected this to happen with tightly coupled customer-customizable chiplets inside a single package, instead. But it seems that packaging is also better left to Intel and AMD, I guess.

IshKebabtoday at 6:25 PM

> Multiple prototype designs could be grouped together

They do this, it's called a multi-project wafer (it's on Wikipedia). It doesn't help with lead time of course. As far as I know tape-out cost is a lot cheaper (if your design is microcontroller-scale) but still in the $100k+ region.

jdw64today at 3:25 PM

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