No, I mean the API should support "useless" code where it makes sense, not that you should manually write it. I don't actually think it applies in this case, but just as a general principle.
A classic example of where they didn't do this right is SystemVerilog arrays. You cannot have busses with zero wires in them. "Why would you need that?" somebody probably said... What's the point of a bus with no wires? Well imagine you write a SystemVerilog module with some memory interface like this:
module foo (
input var logic [31:0] i_addr,
input var logic [7:0] i_data,
input var logic [3:0] i_user_data,
...
But now you want to make it generic. No problem! module foo #(
parameter A = 32,
parameter D = 8,
parameter U = 4
) (
input var logic [(A-1):0] i_addr,
input var logic [(D-1):0] i_data,
input var logic [(U-1):0] i_user_data,
Now suppose you don't have any user data. You set U=0, but that gives `logic [-1:0]` which is invalid because they made the incorrect decision to use closed interval syntax. In fairness Verilog is very old so maybe it wasn't so obvious back then that you always use 0-based indexing with right-open intervals.
> I mean the API should support "useless" code where it makes sense, not that you should manually write it.
There is the conflict - if I write useless code I want the compiler to stop me. This is very different from generic code where sometimes a part simplifies to useless code in some particular context even though the whole is useful. Anytime the system can tell the difference between these two I want them treated different.
Telling the difference between useless code and generic code that has a useless form in this context is often not a solvable problem. There are also cases where if we had known better 40 years ago we would have made a different choice, but it is too late now. However I think the rules stands: the system should reject useless code when that is what someone writes even if the code otherwise parses correctly.