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cpldcpuyesterday at 7:28 PM1 replyview on HN

I had Opus 4.5 design an LLM inference engine in verilog, including firmware and automated verification a while ago: https://github.com/cpldcpu/smollm.c

It's of course far from optical. But lowering the implementation through the abstraction levels turned out to be extremely powerful.


Replies

smetannikyesterday at 7:39 PM

Can you suggest some tutorials for Verilog and FPGAs in general?

I have a spare Tang Nano 9k but I don't feel confident about blindly asking Claude to vibecode me a solution and still would like to have at-least a basic level of understanding.

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