alt Hacker NewsYou're not the first person to say so (and I don't mean to dispute it), but I have never been able to find a clear answer for /why/ those processes are incompatible.
Is it built in different silicon, is it physical steps that's incompatible (ie its actually incompatible), is it different physical preparations that needs to be made (making it economically infeasible to combine)
I cannot help but wonder, even if the answer doesn't change anything in my life.
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Medium ELI5 answer: each company and to a great extent each individual fab has a slightly different recipe, which is known as a "process node". This defines all the fabrication steps, every individual layer and its chemical/physical processing.
This in turn affects the electrical properties: parasitic resistance/capacitance, gate dielectric properties and so on. The dielectric in particular is critically different between DRAM and regular CMOS, because DRAM needs to minimise leakage (as that determines how long the memory lasts between refresh cycles).
Regular factories will retool somewhat between jobs. Because it is quite difficult to finetune a silicon process node, it is more common that a fab will set up for a particular node and then switch to "do not touch or change anything under any circumstances", as doing so may wreck yields.
("different substrate entirely" does exist: that's GaN, for power transistors in phone chargers, and SiC, for even higher power transistors.)
https://www.reddit.com/r/Semiconductors/comments/r1dqmw/how_...
A Reddit user explains a bit here.
The physical structure is completely different. Just compare DRAM ([0]) with compute ([1]). As a result, the production process is completely different.
If you want to know more, the Asianometry youtube channel has some fairly good deep dives, such as [2] going through a decent bunch of the 45nm production process, or [3] doing the same for (early) DRAM.
[0]: https://www.youtube.com/watch?v=Bln-v9LmZ3E
[1]: https://i1.wp.com/semiengineering.com/wp-content/uploads/201...
from my basic understanding, memory is much easier to produce then logic chips like GPUs and CPUs, they don't need that many photolithographic layers. while it could be possible to produce memory in fabs for CPUs (though not really desirable in regard to costs) the other way round is more difficult
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> but I have never been able to find a clear answer for /why/ those processes are incompatible.
You can't find an explanation why they're different for the same reason you can't find an explanation why writing poetry and riding a unicycle isn't the same process.
To add to the other comments…
At a very abstract level, when you're manufacturing DRAM you need to manufacture a lot of circuit elements that have HIGH capacitance, since a DRAM cell is basically a capacitor and the higher its capacitance the less frequently it needs to be refreshed.
On the other hand, when manufacturing logic (CPU/GPU/ASIC) you want to minimize the capacitance of almost all circuit elements, since capacitance introduces delay and switching energy cost.
Nearly everything about the manufacturing processes for DRAM and logic is optimized around this fundamentally incompatible figure of merit.
I worked on the development of Intel's eDRAM process, which was used to integrate DRAM into the CPU/GPU die for Iris Pro embedded graphics from 2013-23. https://ieeexplore.ieee.org/document/6576667/