By adding a bunch of IP blocks that do stuff the open ISA doesn't, like peripherals or multicore processing. It also helps if you can make it high throughout, low latency, or low power by adjusting some "knobs".
The article is quite weak, to be honest. Which is a shame, sillicon IP design is quite an interesting domain and it would deserve better coverage.
I was pleasantly surprised it's a startup done by two of my conationals.
The HN article title suggests a contradiction where there isn't one. The instruction set is just the spec -- the high-level contract that the silicon must implement, with many important details like cycle counts per instruction left unspecified. It implies very little about how you would actually implement the inner workings, which could be done in an almost infinite number of different ways (including simulating them on some completely different architecture). Compare "How do you sell a calculator design when the rules of arithmetic are free?"
You sell the use case and support.
The credibility point is the most interesting part of this. In semiconductors, having a good design seems secondary to convincing customers that you'll still be around to support it years later. RISC-V lowers the barrier to building a CPU, but i'm not sure it lowers the trust barrier nearly as much.