TigerBeetle Core System Architecture: Deconstructing Performance Engineering

> Unlike C++, which allows implicit memory allocations and complex copy constructors

It is trivial to ensure this doesn't happen at compile-time. If you are doing DMA as in the article these guarantees are required.

I really wish they turned it into a dependency or database framework where users could define their own business logic to swap out the double entry accounting, while reusing all the system architecture and networking features, consensus etc.

Sort of like a new paradigm where opinionated custom databases could be created with arbitrary entry logic built on this stack.

Joran from TigerBeetle here! I created TB. Happy to answer questions!

"By [...] utilizing a single-threaded execution loop, TigerBeetle aligns its software architecture perfectly with the physical realities of modern hardware."

Can someone explain why single-threaded execution loop is more aligned with the physical realities of modern hardware ?

Their simulation is fantastic:

https://sim.tigerbeetle.com

Amazing writing, very accessible too.

So batching requests is always something I think should increase performance by a lot, but most server implementations make this pretty difficult, but the thing I struggle the most to understand is how to keep the latency down if you have multiple clients request all batched together? The total amount of latency for all clients is always the latency for the slowest.

Is it just me or does it not seem like this whole article was llm generated?

The two "sources" are fake links that lead to 404s