In the equivalent AMD/Xilinx parts (Zynq), you connect up all the hard IP macros using the FPGA fabric.
If the hard cores are configured with incorrect cache coherency options you may not be able to correct the issue in fpga fabric.
But this is pure speculation, I haven't checked Cyclone V documentation myself.
alt Hacker News
If the hard cores are configured with incorrect cache coherency options you may not be able to correct the issue in fpga fabric.
But this is pure speculation, I haven't checked Cyclone V documentation myself.