Well, it turns out they actually are bothering – while in DDR thru DDR4, the mode registers are write-only, LPDDR2 onwards have an MRR (Mode Register Read) command, which the CPU/chipset can use to inspect the manufacturer and capacity; and DDR5 has copied the same facility from LPDDR.
alt Hacker News
Well, it turns out they actually are bothering – while in DDR thru DDR4, the mode registers are write-only, LPDDR2 onwards have an MRR (Mode Register Read) command, which the CPU/chipset can use to inspect the manufacturer and capacity; and DDR5 has copied the same facility from LPDDR.