Interesting. Since this was implemented on the S3, which uses the ISA XTensa LX instead of the RISC-V of most newer ESP32 series chips, I looked into how Espressif is handling SIMD on the latter ISA. Apparently it is only present in limited fashion as a processor extension on the P4 and S31 [0]. The S31 datasheet claims SIMD [1] and the P4 datasheet [2] files them as "Processor Instruction Extensions."

0. https://bitbanksoftware.blogspot.com/2026/04/esp32-p4-simd-e...

1. https://documentation.espressif.com/esp32-s31_datasheet_en.p...

2. https://documentation.espressif.com/esp32-p4_technical_refer...