Cute but wouldn't work with ssize_t :)

VHDL's array/vector syntax actually works a similar way:

-- gives 0, 1, 2, 3:

for i in 0 to 3 loop

-- gives 3, 2, 1, 0:

for i in 3 downto 0 loop

-- Source - https://stackoverflow.com/a/7642026 -- Posted by Kerrek SB -- Retrieved 2026-10-29, License - CC BY-SA 3.0