True, just writing some SystemVerilog that can be simulated does not guarantee working hardware. The OP does point out that he took it all the way to a netlist targeting a real hardware library. Place and route and actual fabrication, or building it for an FPGA and testing there are still needed to fully prove the design, but if the synthesis tools he used are reliable then there's not a lot of room for it to fail at this point. The clock speed is based on the netlist only, so it'll probably not be that fast after actual place and route, so it'll probably have to be clocked a little slower than 500 MHz, but it should work