> you’d have to drop support for multiple voltage rails and thus multiple IO standards, which is exactly what you don’t want to lose.

Yes? Yes it is? 9 times out of 10, my entire board is LVCMOS33. I would love to have the option to drop all of the power rail complexity in a simplified series of parts.

Sometimes you need maximum I/O speed. Sometimes you need maximum I/O flexibility. Sometimes you need processing horsepower. And sometimes you need the certainty of hardware timing, which you get on a gate array and don't get any time there's a processor involved. Or, often, what I actually need is just a little bit of weird logic that's asynchronous, but too hard to do with the remnants of 74-series or 4000-series logic that are still available.

> Building bitstreams is IMO not complicated. (I just copy a Makefile from a previous project and go from there.)

It is not complicated for people who have spent a long time learning and who have past designs they can copy from. (I have a few of those myself.) It is nasty to explain to a new person and very nasty to explain well enough to reproduce in the future without me around.

> Loading them is a matter of plugging in a JTAG cable and typing “make program”.

Yes, for you on the bench. Now program them into a product on an assembly line. Of course it is possible. It is still a giant headache, and quite a bit worse than just dealing with an MCU.

> I don’t know what you mean with the “manage SW projects for”?

Two words: Xilinx ISE.