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Arm's Cortex X925: Reaching Desktop Performance

136 pointsby ingvetoday at 7:34 AM65 commentsview on HN

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pdpitoday at 9:02 AM

Kind of weird to see an article about high-performance ARM cores without a single reference to Apple or how this hardware compares to M4 or M5 cores.

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Incipienttoday at 9:24 AM

Without being a cpu geek, a lot of the branch prediction details go over my head, however generally a good review. I liked the detail of performance on more complex workloads where IPC can get muddy when you need more instructions.

I feel these days however, for any comparison of performance, power envelope needs to be included (I realise this is dependent on the final chip)

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dinglotoday at 9:24 AM

If ARM starts dominating in desktop and laptop spaces with a quite different set of applications, might we start seeing more software bugs around race conditions? Caused by developers writing software with X86 in mind, with its differing constraints on memory ordering.

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xaropetoday at 10:03 AM

I can't seem to find any power draw or efficiency figures (e.g. <perf>/watts).

Only found this which talks about performance-per-area (PPA) and performance-per-clock ()I assume cycle) (PPC): https://www.reddit.com/r/hardware/comments/1gvo28c/latest_ar...

Supersaiyan_IVtoday at 11:22 AM

Another good read is about ARM's SVE2 extensions: https://gist.github.com/zingaburga/805669eb891c820bd220418ee...

It has some interesting conclusions, such as that it covers certain AVX512 gaps:

"AVX512 plugs many of the holes that SSE had, whilst SVE2 adds more complex operations (such as histogramming and bit permutation), and even introduces new ‘gaps’ (such as 32/64-bit element only COMPACT, no general vector byte left-shift, non-universal predication etc)."

And also that rusty x86 developers might face skill issues:

"Depending on your application, writing code for SVE2 can bring about new challenges. In particular, tailoring fixed-width problems and swizzling data around vectors may become much more difficult when the length is unknown."

sylwaretoday at 10:40 AM

But with hardware IP locks like x86_64.

Better favor as much as possible RISC-V implementations.

But, I don't know if there are already good modern-desktop-grade RISC-V implementations (in the US, Sifive is moving fast as far as I know)... and the hard part: accessing the latest and greatest silicon process of TMSC, aka ~5GHz.

Those markets are completely saturated, namely at best, it will be very slow unless something big does happen: for instance AMD adapts its best micro-architecture to RISC-V (ISA decoding mostly), etc.

And if valve start to distribute a client with a strong RISC-V game compilation framework...

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ddtaylortoday at 9:08 AM

Can't zoom any of the content on mobile so most of the charts are unreadable.

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