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bluGill • today at 11:31 AM • 1 reply • view on HN

The counter is useless code often is a sign of a bug. Possibly someone started implementing something and then failed to finish it. I often want my compiler to warn on useless code.

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IshKebab • today at 12:04 PM

No, I mean the API should support "useless" code where it makes sense, not that you should manually write it. I don't actually think it applies in this case, but just as a general principle.

A classic example of where they didn't do this right is SystemVerilog arrays. You cannot have busses with zero wires in them. "Why would you need that?" somebody probably said... What's the point of a bus with no wires? Well imagine you write a SystemVerilog module with some memory interface like this:

  module foo (
    input var logic [31:0] i_addr,
    input var logic [7:0] i_data,
    input var logic [3:0] i_user_data,
  ...
But now you want to make it generic. No problem!

  module foo #(
    parameter A = 32,
    parameter D = 8,
    parameter U = 4
  ) (
    input var logic [(A-1):0] i_addr,
    input var logic [(D-1):0] i_data,
    input var logic [(U-1):0] i_user_data,
Now suppose you don't have any user data. You set U=0, but that gives `logic [-1:0]` which is invalid because they made the incorrect decision to use closed interval syntax. In fairness Verilog is very old so maybe it wasn't so obvious back then that you always use 0-based indexing with right-open intervals.
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