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85.3 GFlops: Optimizing FP32 Matrix Multiplication on a Single AMD Zen 3 Core

77 pointsby houslastlast Friday at 2:24 PM18 commentsview on HN

Comments

gitowiecyesterday at 8:20 PM

What's the language? My Firefox detected it as English, I suppose it is because of lang=en in HTML

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adrian_byesterday at 8:57 PM

What is interesting here is that this is an optimization study, whose goal was to determine the optimum implementation variant for matrix multiplication on a Zen 3 CPU.

It is likely that a similar optimization strategy would work for a modern Zen 5, though some of the parameters for the optimum variant would probably have double values, because Zen 5 has twice more registers, each double in size, and it can process and transfer a double number of FP32 per clock cycle.

The value given by the author of 63.5% of the theoretical maximum throughput, is likely to be pessimistic, because when doing heavy computations the clock frequency of the CPU will drop, so the actual efficiency might be higher, e.g. perhaps of 70% to 80% of the theoretical maximum throughput at that clock frequency.

The ATLAS BLAS-compatible library attempted to perform automatically such an optimization for its host computer, but I have not studied it to see whether its optimization methods would still work on modern CPUs with AVX+FMA or with AVX-512.

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ranger_dangeryesterday at 8:13 PM

For comparison, the best performing GPUs today can do FP32 at > 100 TFLOP/s

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Razenganyesterday at 9:31 PM

Could alternative CPU architectures like ternary/quaternary and/or analog etc be better at matrix multiplication?

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houslastlast Friday at 2:24 PM

Pushing the Limits of AMD Zen 3: Achieving 85.3 GFLOPS on a Single Core! I recently took on the challenge of squeezing every drop of performance out of a single AMD Zen 3 core, successfully reaching a blazing-fast 85.3 GFLOPS in FP32 matrix multiplication. By diving deep into low-level software optimization—focusing on advanced SIMD vectorization, strict cache management, and instruction pipelining—I managed to maximize CPU efficiency without relying on multi-threading. This project serves as a powerful proof of concept for high-performance computing (HPC) enthusiasts, proving that deeply optimized code can still unlock incredible hidden potential in modern silicon.