alt Hacker NewsThe article doesn't mention anything about what FPGA image is loaded into the thing.
My guess would be that you can choose how to connect the CPU cores to the cache controller, you might want to run the CPUs independently.
The article doesn't mention anything about what FPGA image is loaded into the thing.
My guess would be that you can choose how to connect the CPU cores to the cache controller, you might want to run the CPUs independently.
This is about the hard macros in Altera Cyclone V FPGA.
I suspect the issue is in how Altera configured the IP. They may simply have disabled some part to save on area.