alt Hacker NewsThis is about the hard macros in Altera Cyclone V FPGA.
I suspect the issue is in how Altera configured the IP. They may simply have disabled some part to save on area.
This is about the hard macros in Altera Cyclone V FPGA.
I suspect the issue is in how Altera configured the IP. They may simply have disabled some part to save on area.
In the equivalent AMD/Xilinx parts (Zynq), you connect up all the hard IP macros using the FPGA fabric.