alt Hacker News> The demo is run on an x86 emulator that records every block of code the CPU actually executes, over the whole demo.
> That recording is translated into C - the original instructions, one for one, with the exact cycle timing of the emulated machine.
What's the advantage of this approach vs cycle-accurate emulation? (I'd guess it can go faster, due to compiler optimization?)
> The result is checked against the emulator event for event: every interrupt, port access and frame at the same moment of emulated time.
It's funny how LLMs leak their test procedure docs into user-facing output.
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Yes, cycle-accurate is very expensive because it prevents optimization. But as described they say they're doing an AOT version of cycle-accurate anyway?
In some ways this is similar to the concurrent-systems problems that memory barriers are a tool to address. Your emulator will come in two halves, a CPU side and a gfx/sfx side, as well as control inputs, and the "intermediate" approach is when you're just trying to preserve the sequence of load/stores between the two with an accuracy relative to frame timing. Maintaining ultra precise timing within a frame imposes more detailed coordination requirements on both sides of the emulation.
> It's funny how LLMs leak their test procedure docs into user-facing output.
You have to constantly fight so hard to not get this. And for the past few months it seems most people do not even care to remove it and have proper user facing docs
> What's the advantage of this approach vs cycle-accurate emulation? (I'd guess it can go faster, due to compiler optimization?)
I don't think anyone is doing it this way because they chose to do it this way. All the AI decomp/recomp projects I've seen recently have done it this way. It just seems an easy way to have an AI brute force "port" something.
Cycle accurate emulation helps little with this era PC demos, because back in 1993 PC hardware performance variation was already massive. From 386SX-16 to Pentium 66 MHz, that's over 20x difference in performance.